Full FPGA scientific calculator built from scratch: custom SystemVerilog soft CPU, BCD microcode firmware, Qt/Verilator simulator, and Quartus synthesis for Cyclone II.
Key Takeaways
The CPU treats 4-bit nibbles as its native word size, matching BCD storage where one decimal digit equals one nibble – eliminating constant bit-shifting in standard byte-oriented CPUs.
Toolchain spans Verilator (simulation), Quartus 13.0 SP1 (FPGA synthesis), Qt 6.9+ (desktop/WebAssembly/Android UI), and a custom Python assembler for microcode.
A live WebAssembly build runs in-browser, with and without a debugger, so the design is testable without hardware.
The calctest/ harness and Pathfinding/Proto/ BCD golden-reference submodule provide command-line hardware verification independent of the FPGA board.
Project is CC BY-NC-SA 4.0 – free to adapt and remix, not for commercial use.
Hacker News Comment Review
The author (@gdevic) confirmed the central design motivation: HP-style calculators operate natively on BCD, and a nibble-wide CPU eliminates the architectural friction of forcing decimal math through byte-oriented datapaths like the Z80 or 6502.
