Warpage, glass fragility, hybrid-bond stress, and substrate uncertainty are now the primary scaling barriers for AI and HPC chip packages, not interconnect density.
Key Takeaways
Warpage is the root failure driver: CTE mismatch between organic substrates and low-CTE silicon worsens as packages grow larger, thinner, and more heterogeneous.
Glass carriers improve flatness and thermal match to silicon but introduce brittleness, edge cracking, and microcracking that conventional tests fail to capture early.
Hybrid bonding yield transitions from defect-driven to stress-driven below 2-3 micron pitch as copper density rises and the interface becomes mechanically constrained.
NVIDIA’s Sandeep Razdan (iMAPS keynote): system architecture, not teraflops per GPU, now drives AI performance, making substrate, bonding interface, and thermal path core design variables.
Substrate shortages are partly a supply problem and partly a signal that it is unclear which platforms can still scale mechanically and economically for advanced AI packages.
Hacker News Comment Review
Discussion is sparse; the main substantive signal is a commenter raising an unresolved structural question about through-glass vias: how metal-filled holes in a brittle glass panel survive thermal cycling and soldering without shattering – the article surfaces the problem but offers no solution path.
No consensus or disagreement on the technical claims; the comment thread does not challenge or extend the iMAPS findings.
Notable Comments
@jeffbee: Asks specifically how TGVs (holes etched in glass, filled with metal, then soldered) avoid shattering – notes the article “acknowledges the issues without suggesting where the solutions might come from.”
